View ST6252BB1_5748921.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

april 1998 1/68 r st62t52b st62t62b/e62b 8-bit otp/eprom mcus with a/d converter, auto-reload timer and eeprom n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 64 bytes (none on st62t52b) n user programmable options n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input n 5 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n 8-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n user configurable power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 cdip16w device eprom (bytes) otp (bytes) eeprom st62t52b 1836 - st62t62b 1836 64 st62e62b 1836 64 1 rev. 2.4
2/68 table of contents 68 2 st62t52b / st62t62b/e62b . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 stack space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 data window register (dwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 data ram/eeprom bank register (drbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.7 eeprom description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.3 . eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 clocks, reset, interrupts and power saving modes . . . . . . . . . . . . . . . . . . . . . 16 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 3.2.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.5 mcu initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 digital watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 digital watchdog register (dwdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.1 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.3 interrupt option register (ior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.3 exit from wait and stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2 safe i/o state switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3 artimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/68 table of contents 3 4.2.1 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.2 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.3 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 4.3 auto-reload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3.1 ar timer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3.2 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3.3 ar timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1 st6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.7 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8 artimer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 st62p52b / st62p62b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.2 listing generation and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 st6252b / st6262b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.2 rom readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.2 listing generation and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4/68 st62t52b st62t62b/e62b 1 general description 1.1 introduction the st62t52b and st62t62b devices is low cost members of the st62xx 8-bit hcmos family of microcontrollers, which is targeted at low to medi- um complexity applications. all st62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals. the st62e62b is the erasable eprom version of the st62t62b device, which may be used to em- ulate the st62t52b and st62t62b devices as well as the st6252b and st6262b rom devices. otp and eprom devices are functionally identi- cal. the rom based versions offer the same func- tionality selecting as rom options the options de- fined in the programmable option byte of the otp/eprom versions. otp devices offer all the advantages of user pro- grammability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. these compact low-cost devices feature a timer comprising an 8-bit counter and a 7-bit program- mable prescaler, an 8-bit auto-reload timer, eeprom data c apability (except st62t52b), an 8-bit a/d converter with 4 analog inputs and a digital watchdog timer, making them well suited for a wide range of automotive, appliance and in- dustrial applications. figure 1. block diagram test nmi interrupt program pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram port a port b timer digital 8 bit core test/v pp 8-bit a/d converter pa4..pa5 / ain pb0, pb2..pb3 / 20 ma sink v dd v ss oscin oscout reset watchdog memory pb6 / artimin / 20 ma sink port c pc2..pc3 / ain autoreload timer pb7 / artimout / 20 ma sink 128 bytes 1836 bytes otp (st62t52b, t62b) 1836 bytes eprom (st62e62b) data eeprom 64 bytes (st62t62b/e62b) 4
5/68 st62t52b st62t62b/e62b 1.2 pin descriptions v dd and v ss . power is supplied to the mcu via these two pins. v dd is the power connection and v ss is the ground connection. oscin and oscout. these pins are internally connected to the on-chip oscillator circuit. a quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active-low reset pin is used to re- start the microcontroller. test/v pp . the test must be held at v ss for nor- mal operation. if test pin is connected to a +12.5v level during the reset phase, the eprom/otp programming mode is entered. nmi. the nmi pin provides the capability for asyn- chronous interruption, by applying an external non maskable interrupt to the mcu. the nmi input is falling edge sensitive. it is provided with an on- chip pullup resistor and schmitt trigger character- istics. pa4-pa5. these 2 lines are organized as one i/o port (a). each line may be configured under soft- ware control as inputs with or without internal pull- up resistors, interrupt generating inputs with pull- up resistors, open-drain or push-pull outputs, ana- log inputs for the a/d converter. pb0, pb2-pb3, pb6-pb7. these 5 lines are or- ganized as one i/o port (b). each line may be con- figured under software control as inputs with or without internal pull-up resistors, interrupt gener- ating inputs with pull-up resistors, open-drain or push-pull outputs. pb6/artimin and pb7/arti- mout are either port b i/o bits or the input and output pins of the artimer. reset state of pb2-pb3 pins can be defined by option either with pull-up or high impedance. pb0, pb2-pb3, pb6-pb7 scan also sink 20ma for direct led driving. pc2-pc3 . these 2 lines are organized as one i/o port (c). each line may be configured under soft- ware control as input with or without internal pull- up resistor, interrupt generating input with pull-up resistor, analog input for the a/d converter, open- drain or push-pull output. figure 2. st62t52b, e62b and t62b pin configuration 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 pb0 v pp /test pb2 pb3 v dd artimin/pb6 pc2/ain pc3/ain pa5/ain pa4/ain artimout/pb7 v ss nmi reset oscout oscin 5
6/68 st62t52b st62t62b/e62b 1.3 memory map 1.3.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the following paragraphs. briefly, program space contains user program code in otp and user vectors; data space con- tains user data in ram and in otp, and stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. figure 3. memory addressing diagram program space program interrupt & reset vectors accumulator data ram bank select window select ram x register y register v register w register data read-only window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh memory memory data read-only memory 6
7/68 st62t52b st62t62b/e62b memory map (contd) 1.3.2 program space program space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit program counter register (pc register). 1.3.2.1 program memory protection the program memory in otp or eprom devices can be protected against external readout of memory by selecting the readout protec- tion option in the option byte. in the eprom parts, readout protection option can be disactivated only by u.v. erasure that also results into the whole eprom context erasure. note: once the readout protection is activated, it is no longer possible, even for sgs-thomson, to gain access to the otp contents. returned parts with a protection set can therefore not be ac- cepted. figure 4. st62t52b/t62b program memory map 0000h reserved * user program memory (otp/eprom) 1836 bytes 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved interrupt vectors nmi vector user reset vector (*) reserved areas should be filled with 0ffh 0880h 087fh 7
8/68 st62t52b st62t62b/e62b memory map (contd) 1.3.3 data space data space accommodates all the data necessary for processing the user program. this space com- prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in otp/eprom. 1.3.3.1 data rom all read-only data is physically stored in program memory, which also accommodates the program space. the program memory consequently con- tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in otp/eprom. 1.3.3.2 data ram/eeprom in st62t52b, t62b and st62e62b devices, the data space includes 60 bytes of ram, the accu- mulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port regis- ters, the peripheral data and control registers, the interrupt option register and the data rom win- dow register (drw register). additional ram and eeprom pages can also be addressed using banks of 64 bytes located be- tween addresses 00h and 3fh. 1.3.4 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. table 1. additional ram / eeprom banks table 2. st62t52b, t62b and st62e62b data memory space device ram eeprom st62t52b 1 x 64 bytes - st62t62b 1 x 64 bytes 1 x 64 bytes ram / eeprom banks 000h 03fh data rom window area 040h 07fh x register 080h y register 081h v register 082h w register 083h data ram 60 bytes 084h 0bfh port a data register 0c0h port b data register 0c1h port c data register 0c2h reserved 0c3h port a direction register 0c4h port b direction register 0c5h port c direction register 0c6h reserved 0c7h interrupt option register 0c8h* data rom window register 0c9h* reserved 0cah 0cbh port a option register 0cch port b option register 0cdh port c option register 0ceh reserved 0cfh a/d data register 0d0h a/d control register 0d1h timer prescaler register 0d2h timer counter register 0d3h timer status control register 0d4h ar timer mode control register 0d5h ar timer status/control register1 0d6h ar timer status/control register2 0d7h watchdog register 0d8h ar timer reload/capture register 0d9h ar timer compare register 0dah ar timer load register 0dbh oscillator control register 0dch* miscellaneous 0ddh reserved 0deh 0e7h data ram/eeprom register 0e8h* reserved 0e9h eeprom control register 0eah reserved 0ebh 0feh accumulator 0ffh * write only register 8
9/68 st62t52b st62t62b/e62b memory map (contd) 1.3.5 data window register (dwr) the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes located anywhere in program memory, be- tween address 0000h and 0fffh (top memory ad- dress depends on the specific device). all the pro- gram memory can therefore be used to store either instructions or read-only data. indeed, the window can be moved in steps of 64 bytes along the pro- gram memory by writing the appropriate code in the data window register (dwr). the dwr can be addressed like any ram loca- tion in the data space, it is however a write-only register and therefore cannot be accessed using single-bit operations. this register is used to posi- tion the 64-byte read-only data window (from ad- dress 40h to address 7fh of the data space) in program memory in 64-byte steps. the effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the con- tent of the dwr register (as most significant bits), as illustrated in figure 5 below. for instance, when addressing location 0040h of the data space, with 0 loaded in the dwr register, the physical location addressed in program memory is 00h. the dwr register is not cleared on reset, therefore it must be written to prior to the first ac- cess to the data read-only memory window area. data window register (dwr) address: 0c9h write only bits 6, 7 = not used. bit 5-0 = dwr5-dwr0: data read-only memory window register bits. these are the data read- only memory window bits that correspond to the upper bits of the data read-only memory space. caution: this register is undefined on reset. nei- ther read nor single bit instructions may be used to address this register. note: care is required when handling the dwr register as it is write only. for this reason, the dwr contents should not be changed while exe- cuting an interrupt service routine, as the service routine cannot save and then restore the registers previous contents. if it is impossible to avoid writ- ing to the dwr during the interrupt service rou- tine, an image of the register must be saved in a ram location, and each time the program writes to the dwr, it must also write to the image regis- ter. the image register must be written first so that, if an interrupt occurs between the two instruc- tions, the dwr is not affected. figure 5. data read-only memory window memory addressing 70 - - dwr5 dwr4 dwr3 dwr2 dwr1 dwr0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 0 1 vr01573c 12 1 0 data space address : : 59h 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 000 00 00 1 rom address:a19h 11 13 0 1 9
10/68 st62t52b st62t62b/e62b memory map (contd) 1.3.6 data ram/eeprom bank register (drbr) address: e8h write only bit 7-5 = these bits are not used bit 4 - drbr4 . this bit, when set, selects ram page 2. bit 1-3. not used bit 0. drbr0 . this bit, when set, selects eep- rom page 0. the selection of the bank is made by program- ming the data ram bank switch register (drbr register) located at address e8h of the data space according to table 1. no more than one bank should be set at a time. the drbr register can be addressed like a ram data space at the address e8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. this register is used to se- lect the desired 64-byte ram bank of the data space. the number of banks has to be loaded in the drbr register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3fh address). this register is not cleared during the mcu initial- ization, therefore it must be written before the first access to the data space bank region. refer to the data space description for additional informa- tion. the drbr register is not modified when an interrupt or a subroutine occurs. notes : care is required when handling the drbr register as it is write only. for this reason, it is not allowed to change the drbr contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. if it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to drbr it must write also to the image register. the image register must be written first, so if an interrupt occurs between the two instructions the drbr is not affected. in drbr register, only 1 bit must be set. other- wise two or more pages are enabled in parallel, producing errors. table 3. data ram bank register set-up 70 --- drbr 4 --- drbr 0 drbr st62t52b st62t62b 00 none none 01 not available eeprom page 0 02 not available not available 08 not available not available 10h ram page 2 ram page 2 other reserved reserved 10
11/68 st62t52b st62t62b/e62b memory map (contd) 1.3.7 eeprom description eeprom memory is located in 64-byte pages in data space. this memory may be used by the user program for non-volatile data storage. data space from 00h to 3fh is paged as described in table 4 . row arrangement for parallel writing of eeprom locations . eeprom locations are accessed directly by addressing these paged sec- tions of data space. the eeprom does not require dedicated instruc- tions for read or write access. once selected via the data ram bank register, the active eeprom page is controlled by the eeprom control regis- ter (eectl), which is described below. bit e20ff of the eectl register must be reset prior to any write or read access to the eeprom. if no bank has been selected, or if e2off is set, any ac- cess is meaningless. programming must be enabled by setting the e2ena bit of the eectl register. the e2busy bit of the eectl register is set when the eeprom is performing a programming cycle. any access to the eeprom when e2busy is set is meaningless. provided e2off and e2busy are reset, an eep- rom location is read just like any other data loca- tion, also in terms of access time. writing to the eeprom may be carried out in two modes: byte mode (bmode) and parallel mode (pmode). in bmode, one byte is accessed at a time, while in pmode up to 8 bytes in the same row are programmed simultaneously (with conse- quent speed and power consumption advantages, the latter being particularly important in battery powered circuits). general notes : data should be written directly to the intended ad- dress in eeprom space. there is no buffer mem- ory between data ram and the eeprom space. when the eeprom is busy (e2busy = 1) eectl cannot be accessed in write mode, it is only possible to read the status of e2busy. this implies that as long as the eeprom is busy, it is not possible to change the status of the eeprom control register. eectl bits 4 and 5 are reserved and must never be set. care is required when dealing with the eectl reg- ister, as some bits are write only. for this reason, the eectl contents must not be altered while ex- ecuting an interrupt service routine. if it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to eectl it must also write to the image register. the image regis- ter must be written to first so that, if an interrupt oc- curs between the two instructions, the eectl will not be affected. table 4. . row arrangement for parallel writing of eeprom locations dataspace addresses. banks 0 and 1. byte01234567 row7 38h-3fh row6 30h-37h row5 28h-2fh row4 20h-27h row3 18h-1fh row2 10h-17h row1 08h-0fh row0 00h-07h up to 8 bytes in each row may be programmed simultaneously in parallel write mode. the number of available 64-byte banks (1 or 2) is device dependent. 11
12/68 st62t52b st62t62b/e62b memory map (contd) additional notes on parallel mode: if the user wishes to perform parallel program- ming, the first step should be to set the e2par2 bit. from this time on, the eeprom w ill be ad- dressed in write mode, the row address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting e2par2 without programming the eeprom. af- ter the row address is latched, the mcu can only see the selected eeprom row and any attempt to write or read other rows will produce errors. the eeprom s hould not be read while e2par2 is set. as soon as the e2par2 bit is set, the 8 volatile row latches are cleared. from this moment on, the user can load data in all or in part of the row. setting e2par1 will modify the eeprom regis- ters corresponding to the row latches accessed after e2par2. for example, if the software sets e2par2 and accesses the eeprom by writing to addresses 18h, 1ah and 1bh, and then sets e2par1, these three registers will be modified si- multaneously; the remaining bytes in the row will be unaffected. note that e2par2 is internally reset at the end of the programming cycle. this implies that the user must set the e2par2 bit between two parallel pro- gramming cycles. note that if the user tries to set e2par1 while e2par2 is not set, there will be no programming cycle and the e2par1 bit will be un- affected. consequently, the e2par1 bit cannot be set if e2ena is low. the e2par1 bit can be set by the user, only if the e2ena and e2par2 bits are also set. eeprom control register (eectl) address: eah read/write reset status: 00h bit 7 = d7 : unused. bit 6 = e2off : stand-by enable bit. write only. if this bit is set the eeprom is disabled (any access will be meaningless) and the power consumption of the eeprom is reduced to its lowest value. bit 5-4 = d5-d4 : reserved. must be kept reset. bit 3 = e2par1 : parallel start bit. write only. once in parallel mode, as soon as the user software sets the e2par1 bit, parallel writing of the 8 adja- cent registers will start. this bit is internally reset at the end of the programming procedure. note that less than 8 bytes can be written if required, the un- defined bytes being unaffected by the parallel pro- gramming cycle; this is explained in greater detail in the additional notes on parallel mode overleaf. bit 2 = e2par2 : parallel mode en. bit. write only. this bit must be set by the user program in order to perform parallel programming. if e2par2 is set and the parallel start bit (e2par1) is reset, up to 8 adjacent bytes can be written simultane- ously. these 8 adjacent bytes are considered as a row, whose address lines a7, a6, a5, a4, a3 are fixed while a2, a1 and a0 are the changing bits, as illustrated in table 4. e2par2 is automatically reset at the end of any parallel programming pro- cedure. it can be reset by the user software before starting the programming procedure, thus leaving the eeprom registers unchanged. bit 1 = e2busy : eeprom busy bit. read on- ly. this bit is automatically set by the eeprom control logic when the eeprom is in program- ming mode. the user program should test it be- fore any eeprom read or write operation; any at- tempt to access the eeprom while the busy bit is set will be aborted and the writing procedure in progress will be completed. bit 0 = e2ena : eeprom enable bit. write on- ly. this bit enables programming of the eeprom cells. it must be set before any write to the eep- rom register. any attempt to write to the eep- rom when e2ena is low is meaningless and will not trigger a write cycle. 70 d7 e2o ff d5 d4 e2pa r1 e2pa r2 e2bu sy e2e na 12
13/68 st62t52b st62t62b/e62b 1.4 programming modes 1.4.1 option byte the option byte allows configuration capability to the mcus. option bytes content is automatically read, and the selected options enabled, when the chip reset is activated. it can only be accessed during the programming mode. this access is made either automatically (copy from a master device) or by selecting the option byte programming mode of the programmer. the option byte is located in a non-user map. no address has to be specified. eprom code option byte protect . this bit allows the protection of the software contents against piracy. when the bit protect is set high, readout of the otp con- tents is prevented by hardware. no programming equipment is able to gain access to the user pro- gram. when this bit is low, the user program can be read. extcntl . this bit selects the external stop mode capability. when extcntl is high, pin nmi controls if the stop mode can be accessed when the watchdog is active. when extcntl is low, the stop instruction is processed as a wait as soon as the watchdog is active. pb2-3 pull . when set this bit removes pull-up at reset on pb2-pb3 pins. when cleared pb2-pb3 pins have an internal pull-up resistor at reset. d4 . reserved. must be cleared to zero. wdact . this bit controls the watchdog activation. when it is high, hardware activation is selected. the software activation is selected when wdact is low. delay . this bit enables the selection of the delay internally generated after pin r eset is released. when delay is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when delay is high. oscil . when this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. when it is high, the os- cillator must be controlled by an rc network, with only the resistor having to be externally provided. d0 . reserved. must be cleared to zero. the option byte is written during programming ei- ther by using the pc menu (pc driven mode) or automatically (stand-alone mode) 1.4.2 program memory eprom/otp programming mode is set by a +12.5v voltage applied to the test/v pp pin. the programming flow of the st62t62b is described in the user manual of the eprom programming board. the mcus can be programmed with the st62e6xb eprom programming tools available from sgs-thomson. table 5. st62t52b/t62b program memory map note : otp/eprom devices can be programmed with the development tools available from sgs-thomson (st62e6x-epb or st626x-kit). 1.4.3 . eeprom data memory eeprom data pages are supplied in the virgin state ffh. partial or total programming of eep- rom data memory can be performed either through the application software or through an ex- ternal programmer. any sgs-thomson tool used for the program memory (otp/eprom) can also be used to program the eeprom data mem- ory. 70 pro- tect extc- ntl pb2-3 pull - wdact delay oscil - device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector 13
14/68 st62t52b st62t62b/e62b 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe- ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 6 ; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe- ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg- isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad- dressed in the data space as ram locations at ad- dresses 80h (x) and 81h (y). they can also be ac- cessed with the direct, short direct, or bit direct ad- dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg- ister of the data space. short direct registers (v, w). these two regis- ters are used to save a byte in short direct ad- dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di- rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis- ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper- and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 6st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address/read line data space interrupts data ram/eeprom data rom/eprom results to data space (write line) rom/eprom dedications accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811 14
15/68 st62t52b st62t62b/e62b cpu registers (contd) however, if the program space contains more than 4096 bytes, the additional memory in pro- gram space can be addressed by using the pro- gram bank switch register. the pc value is incremented after reading the ad- dress of the current instruction. to execute rela- tive jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instructionpc=jump address - call instructionpc= call address - relative branch instruction.pc= pc +/- offset - interrupt pc=interrupt vector - resetpc= reset vector - ret & reti instructionspc= pop (stack) - normal instructionpc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur- ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn- mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in- struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou- tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc- curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partic- ipates in the rotate left instruction. the zero flag is set if the result of the last arithme- tic or logical operation was equal to zero; other- wise it is cleared. switching between the three sets of flags is per- formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard- ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter- rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first level register is shift- ed back into the pc and the value of each level is popped back into the previous level. since the ac- cumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. the stack will remain in its deepest position if more than 6 nested calls or interrupts are executed, and consequently the last return ad- dress will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 7st6 cpu programming mode l short direct addressing mode vregister wregister program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator y reg. pointer x reg. pointer cz cz 15
16/68 st62t52b st62t62b/e62b 3 clocks, reset, interrupts and power saving modes 3.1 clock system the mcu features a main oscillator which can be driven by an external clock, or used in conjunction with an at-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor (r net ). figure 8. illustrates various possible oscillator con- figurations using an external crystal or ceramic res- onator, an external clock input, an external resistor (r net ). c l1 an c l2 should have a capacitance in the range 12 to 22 pf for an oscillator frequency in the 4-8 mhz range. a programmable divider is provided in order to adjust the internal clock of the mcu to the best power con- sumption and performance trade-off. the internal mcu clock frequency (f int ) drives di- rectly the ar timer while it is divided by 12 to drive the timer, the a/d converter and the watchdog timer, and by 13 to drive the cpu core, as may be seen in figure 9. . with an 8mhz oscillator frequency, the fastest machine cycle is therefore 1.625s. a machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five machine cycles for execution. 3.1.1 main oscillator the oscillator configuration may be specified by se- lecting the appropriate option. when the crys- tal/resonator option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the oscin pin. when the rc network option is selected, the system clock is generated by an external resistor. figure 8. oscillator configurations osc in osc out c l1n c l2 st6xxx crystal/resonator clock crystal/resonator option osc in osc out st6xxx external clock crystal/resonator option nc osc in osc out r net st6xxx rc network rc network option nc 16
17/68 st62t52b st62t62b/e62b clock system (contd) oscillator control registers address: dch write only bit 7-4. these bits are not used. bit 3. reserved. cleared at reset. this bit must be set to 1 by user program to achieve lowest power consumption. bit 2. reserved. must be kept low. rs1-rs0. these bits select the division ratio of the oscillator divider in order to generate the in- ternal frequency. the following selctions are avail- able: note : care is required when handling the oscr register as some bits are write only. for this rea- son, it is not allowed to change the oscr con- tents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. if it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to oscr it must write also to the image register. the image register must be written first, so if an inter- rupt occurs between the two instructions the oscr is not affected. figure 9. clock circuit block diagram 70 ---- oscr 3 oscr 2 rs1 rs0 rs1 rs0 division ratio 0 0 1 1 0 1 0 1 1 2 4 4 main oscillator core : 13 : 12 : 1 timer watchdog por f int adc ar timer oscillator divider rs0, rs1 oscin oscout f osc f osc 17
18/68 st62t52b st62t62b/e62b 3.2 resets the mcu can be reset in three ways: C by the external reset input being pulled low; C by power-on reset; C by the digital watchdog peripheral timing out. 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in the run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con- figured as inputs with pull-up resistors and the main oscillator is restarted. when the level on the reset pin then goes high, the initialization se- quence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up and all inputs and outputs are configured as inputs with pull-up resistors. when the level of the reset pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu at an appropriate stage during the power-on sequence. at the beginning of this se- quence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. the initialization sequence is executed immedi- ately following the internal delay. the internal delay is generated by an on-chip coun- ter. the internal reset line is released 2048 internal clock cycles after release of the external reset. notes: to ensure correct start-up, the user should take care that the reset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency (see recommended op- erating conditions). a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the r eset pin. figure 10. reset and interrupt processing int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/fff no fetch instruction load pc va000427 18
19/68 st62t52b st62t62b/e62b resets (contd) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. this, amongst oth- er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 application notes no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. the por circuit operates dynamically, in that it triggers mcu initialization on detecting the rising edge of v dd . the typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which v dd rises. the por circuit is not designed to supervise static, or slowly rising or falling v dd . 3.2.5 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (lo- cated in program rom starting at address 0ffeh). a jump to the beginning of the user pro- gram must be coded at this address. following a reset, the interrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the initialisation routine should there- fore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the in- itialisation routine, the mcu will continue by processing the instruction immediately following the reti instruction. if, however, a pending inter- rupt is present, it will be serviced. figure 11. reset and interrupt processing figure 12. reset block diagram reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initialization routine va00181 v dd reset 300k w 2.8k w power watchdog reset ck counter reset st6 internal reset f osc reset on reset va0200b 19
20/68 st62t52b st62t62b/e62b resets (contd) table 6. register reset status register address(es) status comment oscillator control register eeprom control register port data registers port direction register port option register interrupt option register timer status/control ar timer mode control register ar timer status/control 1 register ar timer status/control 2register ar timer compare register miscellaneous register 0dch 0eah 0c0h to 0c2h 0c4h to 0c6h 0cch to 0ceh 0c8h 0d4h 0d5h 0d6h 0d7h 0dah 0ddh 00h f int = f osc ; user must set bit3 to 1 eeprom enabled (if available) i/o are input with pull-up i/o are input with pull-up i/o are input with pull-up interrupt disabled timer disabled ar timer stopped x, y, v, w, register accumulator data ram data ram page register data rom window register eeprom a/d result register ar timer load register ar timer reload/capture register 080h to 083h 0ffh 084h to 0bfh 0e8h 0c9h 00h to f3h 0d0h 0dbh 0d9h undefined as written if programmed timer counter register timer prescaler register watchdog counter register a/d control register 0d3h 0d2h 0d8h 0d1h ffh 7fh feh 40h max count loaded a/d in standby 20
21/68 st62t52b st62t62b/e62b 3.3 digital watchdog the digital watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. the watchdog circuit generates a reset when the downcounter reaches zero. user software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. in the event of a software mishap (usu- ally caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be re- loaded periodically. consequently the timer will decrement down to 00h and reset the mcu. in or- der to maximise the effectiveness of the watch- dog function, user software must be written with this concept in mind. watchdog behaviour is governed by two options, known as watchdog activation (i.e. hardware or software) and external stop mode control (see table 7 recom- mended option choices ). in the software option, the watchdog is disa- bled until bit c of the dwdr register has been set. when the watchdog is disabled, low power stop mode is available. once activated, the watchdog cannot be disabled, except by resetting the mcu. in the hardware option, the watchdog is per- manently enabled. since the oscillator will run continuously, low power mode is not available. the stop instruction is interpreted as a wait in- struction, and the watchdog continues to count- down. however, when the external stop mode control option has been selected low power consumption may be achieved in stop mode. execution of the stop instruction is then gov- erned by a secondary function associated with the nmi pin. if a stop instruction is encountered when the nmi pin is low, it is interpreted as wait, as described above. if, however, the stop in- struction is encountered when the nmi pin is high, the watchdog counter is frozen and the cpu en- ters stop mode. when the mcu exits stop mode (i.e. when an in- terrupt is generated), the watchdog resumes its activity. table 7. recommended option choices functions required recommended options stop mode & watchdog external stop mode & hardware watchdog stop mode software watchdog watchdog hardware watchdog 21
22/68 st62t52b st62t62b/e62b digital watchdog (contd) the watchdog is associated with a data space register (digital watchdog register, dwdr, loca- tion 0d8h) which is described in greater detail in section 3.3.1 digital watchdog register (dwdr) . this register is set to 0feh on reset: bit c is cleared to 0, which disables the watchdog; the timer downcounter bits, t0 to t5, and the sr bit are all set to 1, thus selecting the longest watch- dog timer period. this time period can be set to the users requirements by setting the appropriate value for bits t0 to t5 in the dwdr register. the sr bit must be set to 1, since it is this bit which generates the reset signal when it changes to 0; clearing this bit would generate an immediate re- set. it should be noted that the order of the bits in the dwdr register is inverted with respect to the as- sociated bits in the down counter: bit 7 of the dwdr register corresponds, in fact, to t0 and bit 2 to t5. the user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis- ter. the relationship between the dwdr register bits and the physical implementation of the watch- dog timer downcounter is illustrated in figure 13. . only the 6 most significant bits may be used to de- fine the time period, since it is bit 6 which triggers the reset when it changes to 0. this offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8mhz, this is equivalent to timer pe- riods ranging from 384s to 24.576ms). figure 13. watchdog counter control watchdog control register d0 d1 d3 d4 d5 d6 d7 watchdog counter c sr t5 t4 t3 t2 t1 d2 t0 osc ? 12 reset vr02068a ? 2 8 22
23/68 st62t52b st62t62b/e62b digital watchdog (contd) 3.3.1 digital watchdog register (dwdr) address: 0d8h read/write reset status: 1111 1110b bit 0 = c : watchdog control bit if the hardware option is selected, this bit is forced high and the user cannot change it (the watchdog is always active). when the software option is se- lected, the watchdog function is activated by set- ting bit c to 1, and cannot then be disabled (save by resetting the mcu). when c is kept low the counter can be used as a 7-bit timer. this bit is cleared to 0 on reset. bit 1 = sr : software reset bit this bit triggers a reset when cleared. when c = 0 (watchdog disabled) it is the msb of the 7-bit timer. this bit is set to 1 on reset. bits 2-7 = t5-t0 : downcounter bits it should be noted that the register bits are re- versed and shifted with respect to the physical counter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. these bits are set to 1 on reset. 3.3.2 application notes the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog re- lated options should be selected on the basis of a trade-off between application security and stop mode availability. when stop mode is not required, hardware acti- vation without external stop mode con- trol should be preferred, as it provides maxi- mum security, especially during power-on. when stop mode is required, hardware activa- tion and external stop mode control should be chosen. nmi should be high by default, to allow stop mode to be entered when the mcu is idle. the nmi pin can be connected to an i/o line (see figure 14. ) to allow its state to be controlled by software. the i/o line can then be used to keep nmi low while watchdog protection is required, or to avoid noise or key bounce. when no more processing is required, the i/o line is released and the device placed in stop mode for lowest power consumption. when software activation is selected and the watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, wd, #+3 ldi wd, 0fdh 70 t0 t1 t2 t3 t4 t5 sr c 23
24/68 st62t52b st62t62b/e62b digital watchdog (contd) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. in all modes, a minimum of 28 instructions are ex- ecuted after activation, before the watchdog can generate a reset. consequently, user software should load the watchdog counter within the first 27 instructions following watchdog activation (software mode), or within the first 27 instructions executed following a reset (hardware activation). it should be noted that when the gen bit is low (in- terrupts disabled), the nmi interrupt is active but cannot cause a wake up from stop/wait modes. figure 14. a typical circuit making use of the exernal stop mode control feature figure 15. digital watchdog block diagram nmi switch i/o vr02002 rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock 24
25/68 st62t52b st62t62b/e62b 3.4 interrupts the cpu can manage four maskable interrupt sources, in addition to a non maskable interrupt source (top priority interrupt). each source is as- sociated with a specific interrupt vector which contains a jump instruction to the associated in- terrupt service routine. these vectors are located in program space (see table 8 interrupt vector map ). when an interrupt source generates an interrupt request, and interrupt processing is enabled, the pc register is loaded with the address of the inter- rupt vector (i.e. of the jump instruction), which then causes a jump to the relevant interrupt serv- ice routine, thus servicing the interrupt. interrupt sources are linked to events either on ex- ternal pins, or on chip peripherals. several events can be ored on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. the non maskable interrupt request has the high- est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter- rupt each other. if more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. the priority of each interrupt source is fixed. table 8. interrupt vector map 3.4.1 interrupt request all interrupt sources but the non maskable inter- rupt source can be disabled by setting accordingly the gen bit of the interrupt option register (ior). this gen bit also defines if an interrupt source, in- cluding the non maskable interrupt source, can restart the mcu from stop/wait modes. interrupt request from the non maskable interrupt source #0 is latched by a flip flop which is auto- matically reset by the core at the beginning of the non-maskable interrupt service routine. interrupt request from source #1 can be config- ured either as edge or level sensitive by setting accordingly the les bit of the interrupt option register (ior). interrupt request from source #2 are always edge sensitive. the edge polarity can be configured by setting accordingly the esb bit of the interrupt op- tion register (ior). interrupt request from sources #3 & #4 are level sensitive. in edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be- fore being processed. if several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. storage of interrupt requests is not available in level sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execution. at the end of every instruction, the mcu tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri- ate interrupt service routine is executed instead. table 9. interrupt option register description interrupt source priority vector address interrupt source #0 1 (ffch-ffdh) interrupt source #1 2 (ff6h-ff7h) interrupt source #2 3 (ff4h-ff5h) interrupt source #3 4 (ff2h-ff3h) interrupt source #4 5 (ff0h-ff1h) gen set enable all interrupts cleared disable all interrupts esb set rising edge mode on inter- rupt source #2 cleared falling edge mode on inter- rupt source #2 les set level-sensitive mode on in- terrupt source #1 cleared falling edge mode on inter- rupt source #1 others not used 25
26/68 st62t52b st62t62b/e62b iinterrupts (contd) 3.4.2 interrupt procedure the interrupt procedure is very similar to a call procedure, indeed the user can consider the inter- rupt as an asynchronous call procedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re- sult, the user should save all data space registers which may be used within the interrupt routines. there are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. the following list summarizes the interrupt proce- dure: mcu C the interrupt is detected. C the c and z flags are replaced by the interrupt flags (or by the nmi flags). C the pc contents are stored in the first level of the stack. C the normal interrupt lines are inhibited (nmi still active). C the first internal latch is cleared. C the associated interrupt vector is loaded in the pc. warning: in some circumstances, when a maskable interrupt occurs while the st6 core is in normal mode and especially during the execu- tion of an "ldi ior, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the core will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. user C user selected registers are saved within the in- terrupt service routine (normally on a software stack). C the source of the interrupt is found by polling the interrupt flags (if more than one source is asso- ciated with the same vector). C the interrupt is serviced. C return from interrupt (reti) mcu C automatically the mcu switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous pc value from the stack. the interrupt routine usually begins by the identi- fying the device which generated the interrupt re- quest (by polling). the user should save the regis- ters which are used within the interrupt routine in a software stack. after the reti instruction is exe- cuted, the mcu returns to the main routine. figure 16. interrupt processing flow chart instruction fetch instruction execute instruction was the instruction a reti ? ? clear interrupt mask select program flags "pop" the stacked pc ? check if there is an interrupt request and interrupt mask select internal mode flag push the pc into the stack load pc from interrupt vector (ffc/ffd) set interrupt mask no no yes is the core already in normal mode? va000014 yes no yes 26
27/68 st62t52b st62t62b/e62b iinterrupts (contd) 3.4.3 interrupt option register (ior) the interrupt option register (ior) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. this register is write-only and cannot be accessed by single-bit operations. address: 0c8h write only reset status: 00h bit 7, bits 3-0 = unused . bit 6 = les : level/edge selection bit . when this bit is set to one, the interrupt source #1 is level sensitive. when cleared to zero the edge sensitive mode for interrupt request is selected. bit 5 = esb : edge selection bit . the bit esb selects the polarity of the interrupt source #2. bit 4 = gen : global enable interrupt . when this bit is set to one, all interrupts are enabled. when this bit is cleared to zero all the interrupts (exclud- ing nmi) are disabled. when the gen bit is low, the nmi interrupt is ac- tive but cannot cause a wake up from stop/wait modes. this register is cleared on reset. 3.4.4 interrupt sources interrupt sources available on the st62e62b/t62b are summarized in the table 10 with associated mask bit to enable/disable the in- terrupt request. table 10. interrupt requests and mask bits 70 - les esb gen - - - - peripheral register address register mask bit masked interrupt source interrupt vector general ior c8h gen all interrupts, excluding nm i timer tscr1 d4h eti tmz: timer overflow vector 4 a/d converter adcr d1h eai eoc: end of conversion vector 4 ar timer armc d5h ovie cpie eie ovf: ar timer overflow cpf: successful compare ef: active edge on artimin vector 3 port pan orpa-drpa c0h-c4h orpan-drpan pan pin vector 1 port pbn orpb-drpb c1h-c5h orpbn-drpbn pbn pin vector 1 port pcn orpc-drpc c2h-c6h orpcn-drpcn pcn pin vector 2 27
28/68 st62t52b st62t62b/e62b interrupts (contd) figure 17. interrupt block diagram start 1 i q clk clr ff 1 0 mux ior reg. c8h, bit 6 ior reg. c8h, bit 5 ff clr clk q i 2 start timer1 cpie cpf tmz eti int #4 (ff0,1) int #3 (ff2,3) int #2 (ff4,5) int #1 (ff6,7) restart from stop/wait ar timer ef eie ovf ovie va0426p pbe bits bits port b port a pbe pbe dd v single bit enable from register port a,b,c port c start 0 i q clk clr ff bit gen (ior register) nmi (ffc,d) nmi v dd adc eoc eai 28
29/68 st62t52b st62t62b/e62b 3.5 power saving modes the wait and stop modes have been imple- mented in the st62xx family of mcus in order to reduce the products electrical consumption dur- ing idle periods. these two power saving modes are described in the following paragraphs. 3.5.1 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. the microcontroller can be considered as being in a software frozen state where the core stops processing the pro- gram instructions, the ram contents and periph- eral registers are preserved as long as the power supply voltage is higher than the ram retention voltage. in this mode the peripherals are still ac- tive. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing track of time or the capa- bility of monitoring external events. the active os- cillator is not stopped in order to provide a clock signal to the peripherals. timer counting may be enabled as well as the timer interrupt, before en- tering the wait mode: this allows the wait mode to be exited when a timer interrupt occurs. the same applies to other peripherals which use the clock signal. if the wait mode is exited due to a reset (either by activating the external pin or generated by the watchdog), the mcu enters a normal reset proce- dure. if an interrupt is generated during wait mode, the mcus behaviour depends on the state of the processor core prior to the wait instruction, but also on the kind of interrupt request which is generated. this is described in the following para- graphs. the processor core does not generate a delay following the occurrence of the interrupt, be- cause the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 stop mode if the watchdog is disabled, stop mode is avail- able. when in stop mode, the mcu is placed in the lowest power consumption mode. in this oper- ating mode, the microcontroller can be considered as being frozen, no instruction is executed, the oscillator is stopped, the ram contents and pe- ripheral registers are preserved as long as the power supply voltage is higher than the ram re- tention voltage, and the st62xx core waits for the occurrence of an external interrupt request or a reset to exit the stop state. if the stop state is exited due to a reset (by ac- tivating the external pin) the mcu will enter a nor- mal reset procedure. behaviour in response to in- terrupts depends on the state of the processor core prior to issuing the stop instruction, and also on the kind of interrupt request that is gener- ated. this case will be described in the following para- graphs. the processor core generates a delay af- ter occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, be- fore executing the first instruction. 29
30/68 st62t52b st62t62b/e62b power saving mode (contd) 3.5.3 exit from wait and stop modes the following paragraphs describe how the mcu exits from wait and stop modes, when an inter- rupt occurs (not a reset). it should be noted that the restart sequence depends on the original state of the mcu (normal, interrupt or non-maskable in- terrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. interrupts do not affect the oscillator selection. 3.5.3.1 normal mode if the mcu was in the main routine when the wait or stop instruction was executed, exit from stop or wait mode will occur as soon as an interrupt oc- curs; the related interrupt routine is executed and, on completion, the instruction which follows the stop or wait instruction is then executed, pro- viding no other interrupts are pending. 3.5.3.2 non maskable interrupt mode if the stop or wait instruction has been execut- ed during execution of the non-maskable interrupt routine, the mcu exits from the stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is ex- ecuted, and the mcu remains in non-maskable in- terrupt mode, even if another interrupt has been generated. 3.5.3.3 normal interrupt mode if the mcu was in interrupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc- curs. nevertheless, two cases must be consid- ered: C if the interrupt is a normal one, the interrupt rou- tine in which the wait or stop mode was en- tered will be completed, starting with the execution of the instruction which follows the stop or the wait instruction, and the mcu is still in the interrupt mode. at the end of this rou- tine pending interrupts will be serviced in ac- cordance with their priority. C in the event of a non-maskable interrupt, the non-maskable interrupt service routine is proc- essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal interrupt mode. notes: to achieve the lowest power consumption during run or wait modes, the user program must take care of: C configuring unused i/os as inputs without pull-up (these should be externally tied to well defined logic levels); C placing all peripherals in their power down modes before entering stop mode; when the hardware activated watchdog is select- ed, or when the software watchdog is enabled, the stop instruction is disabled and a wait in- struction will be executed in its place. if all interrupt sources are disabled (gen low), the mcu can only be restarted by a reset. although setting gen low does not mask the nmi as an in- terrupt, it will stop it generating a wake-up signal. the wait and stop instructions are not execut- ed if an enabled interrupt request is pending. 30
31/68 st62t52b st62t62b/e62b 4 on-chip peripherals 4.1 i/o ports the mcu features input/output lines which may be individually programmed as any of the follow- ing input or output configurations: C input without pull-up or interrupt C input with pull-up and interrupt C input with pull-up, but without interrupt C analog input C push-pull output C open drain output the lines are organised as bytewise ports. each port is associated with 3 registers in data space. each bit of these registers is associated with a particular line (for instance, bits 0 of port a data, direction and option registers are associat- ed with the pa0 line of port a). the data registers (drx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the dif- ferent input mode options. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is done from i/o pins while writing will direct- ly affect the port data register causing an unde- sired change of the input configuration. the data direction registers (ddrx) allow the data direction (input or output) of each pin to be set. the option registers (orx) are used to select the different port options available both in input and in output mode. all i/o registers can be read or written to just as any other ram location in data space, so no extra ram cells are needed for port data storage and manipulation. during mcu initialization, all i/o registers are cleared and the input mode with pull- ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. figure 18. i/o port block diagram v dd reset s in controls s out shift register data data direction register register option register input/output to interrupt v dd to adc va00413 31
32/68 st62t52b st62t62b/e62b i/o ports (contd) 4.1.1 operating modes each pin may be individually programmed as input or output with various configurations. this is achieved by writing the relevant bit in the data (dr), data direction (ddr) and option reg- isters (or). table 11 i/o port option selection il- lustrates the various port configurations which can be selected by user software. 4.1.1.1 input options pull-up, high impedance option. all input lines can be individually programmed with or without an internal pull-up by programming the or and dr registers accordingly. if the pull-up option is not selected, the input pin will be in the high-imped- ance state. 4.1.1.2 interrupt options all input lines can be individually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software as de- scribed in the interrupt chapter for each port. 4.1.1.3 analog input options some pins can be configured as analog inputs by programming the or and dr registers according- ly. these analog inputs are connected to the on- chip 8-bit analog to digital converter. only one pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively short- ed. table 11. i/o port option selection note: x = dont care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available) 32
33/68 st62t52b st62t62b/e62b i/o ports (contd) 4.1.2 safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom- mended safe transitions are illustrated in figure 19. . all other transitions are potentially risky and should be avoided when changing the i/o operat- ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter- rupt generation or two pins shorted together by the analog multiplexer. single bit instructions (set, res, inc and dec) should be used with great caution on ports data registers, since these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data regis- ter latches. since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit instructions may then be used on the ram copy, after which the whole copy register can be written to the port data regis- ter: set bit, datacopy ld a, datacopy ld dra, a warning: care must also be taken to not use in- structions that act on a whole port register (inc, dec, or read operations) when all 8 bits are not available on the device. unavailable bits must be masked by software (and instruction). the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con- sumption is achieved by configuring i/os in input mode with well-defined logic levels. the user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. figure 19. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111 33
34/68 st62t52b st62t62b/e62b i/o ports (contd) table 12. i/o port option selections note 1 . provided the correct configuration has been selected. mode available on (1) schematic input reset state( reset state if pull-up option disabled pa4-pa5 pb0, pb6-pb7 pc2-pc3 pb2-pb3, input reset state reset state if pull-up option enabled pa4-pa5 pb0,,pb6-pb7 pc2-pc3 pb2-pb3 input with pull up with interrupt pa4-pa5 pb0, pb2-pb3,pb6-pb7 pc2-pc3 analog input pa4-pa5 pc2-pc3 open drain output 5ma open drain output 20ma pa4-pa5 pc2-pc3 pb0, pb2-pb3,pb6-pb7 push-pull output 5ma push-pull output 20ma pa4-pa5 pc2-pc3 pb0, pb2-pb3,pb6-pb7 data in interrupt data in interrupt data in interrupt data out adc data out 34
35/68 st62t52b st62t62b/e62b i/o ports (contd) 4.1.3 artimer alternate functions when bit pwmoe of register armc is low, pin artimout/pb7 is configured as any standard pin of port b through the port registers. when pw- moe is high, artmout/pb7 is the pwm output, independently of the port registers configuration. artimin/pb6 is connected to the ar timer input. it is configured through the port registers as any standard pin of port b. to use artimin/pb6 as ar timer input, it must be configured as input through ddrb. figure 20. peripheral interface configuration of ar timer ar timer artimin pwmoe artimout dr pid dr 1 mux 0 vr01661g artimin artimout pid or 35
36/68 st62t52b st62t62b/e62b 4.2 timer the mcu features an on-chip timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 15 . figure 21. shows the timer block diagram. the content of the 8-bit counter can be read/written in the timer/counter register, tcr, which can be addressed in data space as a ram location at ad- dress 0d3h. the state of the 7-bit prescaler can be read in the psc register at address 0d2h. the control logic device is managed in the tscr reg- ister as described in the following paragraphs. the 8-bit counter is decrement by the output (ris- ing edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer ze- ro)bit in the tscr is set. if the eti (enable timer interrupt) bit in the tscr is also set, an interrupt request is generated. the timer interrupt can be used to exit the mcu from wait mode. the prescaler input is the internal frequency (f int ) divided by 12. the prescaler decrements on the rising edge. depending on the division factor pro- grammed by ps2, ps1 and ps0 bits in the tscr (see table 13. ), the clock input of the timer/coun- ter register is multiplexed to different sources. for division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of tcr. this bit changes its state at half the fre- quency of the prescaler input clock. for factor 4, bit 1 of the psc is connected to the clock input of tcr, and so forth. the prescaler initialize bit, psi, in the tscr register must be set to allow the pres- caler (and hence the counter) to start. if it is cleared, all the prescaler bits are set and the coun- ter is inhibited from counting. the prescaler can be loaded with any value between 0 and 7fh, if bit psi is set. the prescaler tap is selected by means of the ps2/ps1/ps0 bits in the control register. figure 22. illustrates the timers working principle. figure 21. timer block diagram status/control 8 tmz eti d5 d4 psi ps2 ps1 ps0 register 8-bit 1 of 7 select interrupt line / 3 5 6 4 3 2 1 0 psc vr02070a f int b7 b6 b5 b4 b3 b2 b1 b0 8 8 . 12 data bus . 36
37/68 st62t52b st62t62b/e62b timer (contd) 4.2.1 timer operation the timer prescaler is clocked by the prescaler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. 4.2.2 timer interrupt when the counter register decrements to zero with the eti (enable timer interrupt) bit set to one, an interrupt request associated with interrupt vec- tor #3 is generated. when the counter decrements to zero, the tmz bit in the tscr register is set to one. 4.2.3 application notes tmz is set when the counter reaches zero; how- ever, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cleared by user software when servicing the timer interrupt to avoid unde- sired interrupts when leaving the interrupt service routine. after reset, the 8-bit counter register is loaded with 0ffh, while the 7-bit prescaler is load- ed with 07fh, and the tscr register is cleared. this means that the timer is stopped (psi=0) and the timer interrupt is disabled. figure 22. timer working principle bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 2 34 5 67 ps0 ps1 ps2 va00186 37
38/68 st62t52b st62t62b/e62b timer (contd) a write to the tcr register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. 4.2.4 timer registers timer status control register (tscr) address: 0d4h read/write bit 7 = tmz : timer zero bit a low-to-high transition indicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrup when set, enables the timer interrupt request (vector #3). if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is gener- ated. bit 5 = d5 : reserved must be set to 1. bit 4 = d4 do not care. bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its counting. when psi=0 the prescaler is set to 7fh and the counter is inhibited. when psi=1 the prescaler is enabled to count downwards. as long as psi=0 both counter and prescaler are not running. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se- lect. these bits select the division ratio of the pres- caler register. table 13. prescaler division factors timer counter register (tcr) address: 0d3h read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d2h read/write bit 7 = d7 : always read as "0". bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti d5 d4 psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0 0 0 1 0 0 1 2 0 1 0 4 0118 10016 10132 11064 111128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 38
39/68 st62t52b st62t62b/e62b 4.3 auto-reload timer the auto-reload timer (ar timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f int , f int/3 or an external clock source. a mode control register, armc, two status control registers, arsc0 and arsc1, an output pin, artimout, and an input pin, artimin, allow the auto-reload timer to be used in 4 modes: C auto-reload (pwm generation), C output compare and reload on external event (pll), C input capture and output compare for time measurement. C input capture and output compare for period measurement. the ar timer can be used to wake the mcu from wait mode either with an internal or with an ex- ternal clock. it also can be used to wake the mcu from stop mode, if used with an external clock signal connected to the artimin pin. a load reg- ister allows the program to read and write the counter on the fly. 4.3.1 ar timer description the ar counter is an 8-bit up-counter incre- mented on the input clocks rising edge. the coun- ter is loaded from the reload/capture register, arrc, for auto-reload or capture operations, as well as for initialization. direct access to the ar counter is not possible; however, by reading or writing the arlr load register, it is possible to read or write the counters contents on the fly. the ar timers input clock can be either the inter- nal clock (from the oscillator divider), the internal clock divided by 3, or the clock signal connected to the artimin pin. selection between these clock sources is effected by suitably programming bits cc0-cc1 of the arsc1 register. the output of the ar multiplexer feeds the 7-bit programmable ar prescaler, arpsc, which selects one of the 8 available taps of the prescaler, as defined by psc0-psc2 in the ar mode control register. thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). the clock input to the ar counter is enabled by the ten (timer enable) bit in the armc register. when ten is reset, the ar counter is stopped and the prescaler and counter contents are frozen. when ten is set, the ar counter runs at the rate of the selected clock source. the counter is cleared on system reset. the ar counter may also be initialized by writing to the arlr load register, which also causes an immediate copy of the value to be placed in the ar counter, regardless of whether the counter is running or not. initialization of the counter, by ei- ther method, will also clear the arpsc register, whereupon counting will start from a known value. 4.3.2 timer operating modes four different operating modes are available for the ar timer: auto-reload mode with pwm generation. this mode allows a pulse width modulated signal to be generated on the artimout pin with minimum core processing overhead. the free running 8-bit counter is fed by the pres- calers output, and is incremented on every rising edge of the clock signal. when a counter overflow occurs, the counter is automatically reloaded with the contents of the reload/capture register, arcc, and artimout is set. when the counter reaches the value con- tained in the compare register (arcp), artimout is reset. on overflow, the ovf flag of the arsc0 register is set and an overflow interrupt request is generat- ed if the overflow interrupt enable bit, ovie, in the mode control register (armc), is set. the ovf flag must be reset by the user software. when the counter reaches the compare value, the cpf flag of the arsc0 register is set and a com- pare interrupt request is generated, if the com- pare interrupt enable bit, cpie, in the mode con- trol register (armc), is set. the interrupt service routine may then adjust the pwm period by load- ing a new value into arcp. the cpf flag must be reset by user software. the pwm signal is generated on the artimout pin (refer to the block diagram). the frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the re- load/capture register, arrc. the duty cycle of the pwm signal is controlled by the compare register, arcp. 39
40/68 st62t52b st62t62b/e62b auto-reload timer (contd) figure 23. . ar timer block diagram data bus 8 8 8 compare 8 reload/capture data bus ar timer vr01660a 8 8 r s tcld ovie pwmoe ovf load artimout m synchro artimin sl0-sl1 int f pb6/ ar register ef register load ar u x f int /3 ar prescaler 7-bit cc0-cc1 ar counter 8-bit ar compare register ovf eie ef interrupt cpf cpie cpf drb7 ddrb7 pb7/ ps0-ps2 88 40
41/68 st62t52b st62t62b/e62b auto-reload timer (contd) it should be noted that the reload values will also affect the value and the resolution of the duty cy- cle of pwm output signal. to obtain a signal on artimout, the contents of the arcp register must be greater than the contents of the arrc register. the maximum available resolution for the arti- mout duty cycle is: resolution = 1/[255-(arrc)] where arrc is the content of the reload/capture register. the compare value loaded in the com- pare register, arcp, must be in the range from (arrc) to 255. the artc counter is initialized by writing to the arrc register and by then setting the tcld (tim- er load) and the ten (timer clock enable) bits in the mode control register, armc. enabling and selection of the clock source is con- trolled by the cc0, cc1, sl0 and sl1 bits in the status control register, arsc1. the prescaler di- vision ratio is selected by the ps0, ps1 and ps2 bits in the arsc1 register. in auto-reload mode, any of the three available clock sources can be selected: internal clock, in- ternal clock divided by 3 or the clock signal present on the artimin pin. figure 24. . auto-reload timer pwm function counter compare value reload register pwm output t t 255 000 vr001852 41
42/68 st62t52b st62t62b/e62b auto-reload timer (contd) capture mode with pwm generation . in this mode, the ar counter operates as a free running 8-bit counter fed by the prescaler output. the counter is incremented on every clock rising edge. an 8-bit capture operation from the counter to the arrc register is performed on every active edge on the artimin pin, when enabled by edge con- trol bits sl0, sl1 in the arsc1 register. at the same time, the external flag, ef, in the arsc0 register is set and an external interrupt request is generated if the external interrupt enable bit, eie, in the armc register, is set. the ef flag must be reset by user software. each artc overflow sets artimout, while a match between the counter and arcp (compare register) resets artimout and sets the compare flag, cpf. a compare interrupt request is generat- ed if the related compare interrupt enable bit, cpie, is set. a pwm signal is generated on arti- mout. the cpf flag must be reset by user soft- ware. the frequency of the generated signal is deter- mined by the prescaler setting. the duty cycle is determined by the arcp register. initialization and reading of the counter are identi- cal to the auto-reload mode (see previous descrip- tion). enabling and selection of clock sources is control- led by the cc0 and cc1 bits in the ar status control register, arsc1. the prescaler division ratio is selected by pro- gramming the ps0, ps1 and ps2 bits in the arsc1 register. in capture mode, the allowed clock sources are the internal clock and the internal clock divided by 3; the external artimin input pin should not be used as a clock source. capture mode with reset of counter and pres- caler, and pwm generation. this mode is identi- cal to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period meas- urement on the artimin pin). load on external input . the counter operates as a free running 8-bit counter fed by the prescaler. the count is incremented on every clock rising edge. each counter overflow sets the artimout pin. a match between the counter and arcp (compare register) resets the artimout pin and sets the compare flag, cpf. a compare interrupt request is generated if the related compare interrupt enable bit, cpie, is set. a pwm signal is generated on artimout. the cpf flag must be reset by user software. initialization of the counter is as described in the previous paragraph. in addition, if the external ar- timin input is enabled, an active edge on the input pin will copy the contents of the a rrc register into the counter, whether the counter is running or not. notes : the allowed ar timer clock sources are the fol- lowing: the clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. for instance, the multiplexer setting should not be modified while the counter is counting. loading of the counter by any means (by auto-re- load, through arlr, arrc or by the core) resets the prescaler at the same time. care should be taken when both the capture in- terrupt and the overflow interrupt are used. cap- ture and overflow are asynchronous. if the capture occurs when the overflow interrupt flag, ovf, is high (between counter overflow and the flag being reset by software, in the interrupt routine), the ex- ternal interrupt flag, ef, may be cleared simul- taneusly without the interrupt being taken into ac- count. the solution consists in resetting the ovf flag by writing 06h in the arsc0 register. the value of ef is not affected by this operation. if an interrupt has occured, it will be processed when the mcu exits from the interrupt routine (the second interrupt is latched). ar timer mode clock sources auto-reload mode f int , f int/3 , artimin capture mode f int , f int/3 capture/reset mode f int , f int/3 external load mode f int , f int/3 42
43/68 st62t52b st62t62b/e62b auto-reload timer (contd) 4.3.3 ar timer registers ar mode control register (armc) address: d5h read/write reset status: 00h the ar mode control register armc is used to program the different operating modes of the ar timer, to enable the clock and to initialize the counter. it can be read and written to by the core and it is cleared on system reset (the ar timer is disabled). bit 7 = tlcd : timer load bit. this bit, when set, will cause the contents of arrc register to be loaded into the counter and the contents of the prescaler register, arpsc, are cleared in order to initialize the timer before starting to count. this bit is write-only and any attempt to read it will yield a logical zero. bit 6 = ten : timer clock enable. this bit, when set, allows the timer to count. when cleared, it will stop the timer and freeze arpsc and artsc. bit 5 = pwmoe : pwm output enable. this bit, when set, enables the pwm output on the arti- mout pin. when reset, the pwm output is disa- bled. bit 4 = eie : external interrupt enable. this bit, when set, enables the external interrupt request. when reset, the external interrupt request is masked. if eie is set and the related flag, ef, in the arsc0 register is also set, an interrupt re- quest is generated. bit 3 = cpie : compare interrupt enable. this bit, when set, enables the compare interrupt request. if cpie is reset, the compare interrupt request is masked. if cpie is set and the related flag, cpf, in the arsc0 register is also set, an interrupt re- quest is generated. bit 2 = ovie : overflow interrupt . this bit, when set, enables the overflow interrupt request. if ovie is reset, the compare interrupt request is masked. if ovie is set and the related flag, ovf in the arsc0 register is also set, an interrupt re- quest is generated. bit 1-0 = armc1-armc0 : mode control bits 1-0 . these are the operating mode control bits. the following bit combinations will select the various operating modes: ar timer status/control registers arsc0 & arsc1. these registers contain the ar timer status information bits and also allow the program- ming of clock sources, active edge and prescaler multiplexer setting. arsc0 register bits 0,1 and 2 contain the interrupt flags of the ar timer. these bits are read normal- ly. each one may be reset by software. writing a one does not affect the bit value. ar status control register 0 (arsc0) address: d6h read/clear bits 7-3 = d7-d3 : unused bit 2 = ef : external interrupt flag. this bit is set by any active edge on the external artimin input pin. the flag is cleared by writing a zero to the ef bit. bit 1 = cpf : compare interrupt flag. this bit is set if the contents of the counter and the arcp regis- ter are equal. the flag is cleared by writing a zero to the cpf bit. bit 0 = ovf : overflow interrupt flag. this bit is set by a transition of the counter from ffh to 00h (overflow). the flag is cleared by writing a zero to the ovf bit. 70 tcld ten pwmoe eie cpie ovie armc1 armc0 armc1 armc0 operating mode 0 0 auto-reload mode 0 1 capture mode 10 capture mode with reset of artc and arpsc 11 load on external edge mode 70 d7 d6 d5 d4 d3 ef cpf ovf 43
44/68 st62t52b st62t62b/e62b auto-reload timer (contd) ar status control register 1(arsc1) address: d7h read/write bist 7-5 = ps2-ps0 : prescaler division selection bits 2-0. these bits determine the prescaler divi- sion ratio. the prescaler itself is not affected by these bits. the prescaler division ratio is listed in the following table: table 14. . prescaler division ratio selection bit 4 = d4 : reserved . must be kept reset. bit 3-2 = sl1-sl0 : timer input edge control bits 1- 0. these bits control the edge function of the timer input pin for external synchronization. if bit sl0 is reset, edge detection is disabled; if set edge detec- tion is enabled. if bit sl1 is reset, the ar timer input pin is rising edge sensitive; if set, it is falling edge sensitive. bit 1-0 = cc1-cc0 : clock source select bit 1-0. these bits select the clock source for the ar timer through the ar multiplexer. the programming of the clock sources is explained in the following table 15 . clock source selection. : table 15. . clock source selection. ar load register arlr . the arlr load regis- ter is used to read or write the artc counter reg- ister on the fly (while it is counting). the arlr register is not affected by system reset. ar load register (arlr) address: dbh read/write bit 7-0 = d7-d0 : load register data bits. these are the load register data bits. ar reload/capture register . the arrc re- load/capture register is used to hold the auto-re- load value which is automatically loaded into the counter when overflow occurs. ar reload/capture (arrc) address: d9h read/write bit 7-0 = d7-d0 : reload/capture data bits . these are the reload/capture register data bits. ar compare register . the cp compare register is used to hold the compare value for the compare function. ar compare register (arcp) address: dah read/write bit 7-0 = d7-d0 : compare data bits . these are the compare register data bits. 70 ps2 ps1 ps0 d4 sl1 sl0 cc1 cc0 ps2 ps1 ps0 arpsc division ratio 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 sl1 sl0 edge detection x 0 disabled 0 1 rising edge 1 1 falling edge cc1 cc0 clock source 00f int 01f int divided by 3 1 0 artimin input clock 1 1 reserved 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 44
45/68 st62t52b st62t62b/e62b 4.4 a/d converter (adc) the a/d converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate i/o functions (the number of which is device de- pendent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock fre- quency of 8mhz). the adc converts the input voltage by a process of successive approximations, using a clock fre- quency derived from the oscillator with a division factor of twelve. with an oscillator clock frequency less than 1.2mhz, conversion accuracy is de- creased. selection of the input pin is done by configuring the related i/o line as an analog input via the op- tion and data registers (refer to i/o ports descrip- tion for additional information). only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is selected as an analog input si- multaneously, to avoid device malfunction. the adc uses two registers in the data space: the adc data conversion register, adr, which stores the conversion result, and the adc control regis- ter, adcr, used to program the adc functions. a conversion is started by writing a 1 to the start bit (sta) in the adc control register. this auto- matically clears (resets to 0) the end of conver- sion bit (eoc). when a conversion is complete, the eoc bit is automatically set to 1, in order to flag that conversion is complete and that the data in the adc data conversion register is valid. each conversion has to be separately initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to 1 while a previous conversion is in progress, a new conversion is started before com- pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log- ical 0. the a/d converter features a maskable interrupt associated with the end of conversion. this inter- rupt is associated with interrupt vector #4 and oc- curs when the eoc bit is set (i.e. when a conver- sion is completed). the interrupt is masked using the eai (interrupt mask) bit in the control register. the power consumption of the device can be re- duced by turning off the adc peripheral. this is done by setting the pds bit in the adc control register to 0. if pds=1, the a/d is powered and enabled for conversion. this bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the a/d con- verter. this action is also needed before entering wait mode, since the a/d comparator is not auto- matically disabled in wait mode. during reset, any conversion in progress is stopped, the control register is reset to 40h and the adc interrupt is masked (eai=0). figure 25. adc block diagram 4.4.1 application notes the a/d converter does not feature a sample and hold circuit. the analog voltage to be measured should therefore be stable during the entire con- version cycle. voltage variation should not exceed 1/2 lsb for the optimum conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con- version. when selected as an analog channel, the input pin is internally connected to a capacitor c ad of typi- cally 12pf. for maximum accuracy, this capacitor must be fully charged at the beginning of conver- sion. in the worst case, conversion starts one in- struction (6.5 s) after the channel has been se- lected. in worst case conditions, the impedance, asi, of the analog voltage source is calculated us- ing the following formula: 6.5s = 9 x c ad x asi (capacitor charged to over 99.9%), i.e. 30 k w in- cluding a 50% guardband. asi can be higher if c ad has been charged for a longer period by add- ing instructions before the start of conversion (adding more than 26 cpu cycles is pointless). control register converter va00418 result register reset interrupt clock av av dd ain 8 core control signals ss 8 core 45
46/68 st62t52b st62t62b/e62b a/d converter (contd) since the adc is on the same chip as the micro- processor, the user should not switch heavily loaded output signals during conversion, if high precision is required. such switching will affect the supply voltages used as analog references. the accuracy of the conversion depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regu- lated reference voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 5v/ms). this implies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolution is given by:: the input voltage (ain) which is to be converted must be constant for 1s before conversion and remain constant during conversion. conversion resolution can be improved if the pow- er supply voltage (v dd ) to the microcontroller is lowered. in order to optimise conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise distur- bances and power supply variations due to output switching. nevertheless, the wait instruction should be executed as soon as possible after the beginning of the conversion, because execution of the wait instruction may cause a small variation of the v dd voltage. the negative effect of this var- iation is minimized at the beginning of the conver- sion when the converter is less sensitive, rather than at the end of conversion, when the less sig- nificant bits are determined. the best configuration, from an accuracy stand- point, is wait mode with the timer stopped. in- deed, only the adc peripheral and the oscillator are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. it should be noted that waking up the microcontroller could also be done using the timer interrupt, but in this case the timer will be working and the resulting noise could affect conversion accuracy. a/d converter control register (adcr) address: 0d1h read/write bit 7 = eai : enable a/d interrupt. if this bit is set to 1 the a/d interrupt is enabled, when eai=0 the interrupt is disabled. bit 6 = eoc : end of conversion. read only . this read only bit indicates when a conversion has been completed. this bit is automatically reset to 0 when the sta bit is written. if the user is using the interrupt option then this bit can be used as an interrupt pending bit. data in the data conversion register are valid only when this bit is set to 1. bit 5 = sta : start of conversion. write only . writ- ing a 1 to this bit will start a conversion on the se- lected channel and automatically reset to 0 the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. this bit is write on- ly, any attempt to read it will show a logical zero. bit 4 = pds : power down selection. this bit acti- vates the a/d converter if set to 1. writing a 0 to this bit will put the adc in power down mode (idle mode). bit 3-0 = d3-d0. not used a/d converter data register (adr) address: 0d0h read only bit 7-0 = d7-d0 : 8 bit a/d conversion result. v dd v ss C 256 --------------------------- - 70 eaieocstapdsd3d2d1d0 70 d7 d6 d5 d4 d3 d2 d1 d0 46
47/68 st62t52b st62t62b/e62b 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the ability to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro- gram space, data space, and stack space. pro- gram space contains the instructions which are to be executed, plus the data for immediate mode in- structions. data space contains the accumulator, the x,y,v and w registers, peripheral and in- put/output registers, the ram locations and data rom locations (for storage of tables and con- stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme- diate addressing mode is used to access con- stants which do not change during program exe- cution (e.g., a constant used to initialize a loop counter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. direct addressing allows the user to directly ad- dress the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the opcode. short direct addressing is a subset of the direct addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op- code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative ad- dressing mode is only used in conditional branch instructions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. if the condition is not true, the instruction which follows the relative instruc- tion is executed. the relative addressing mode in- struction is one-byte long. the opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which de- termines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub- tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad- dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad- dressing mode is a combination of direct address- ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden- tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro- gram space. the third byte is the jump displace- ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, x or y (80h,81h). the indirect register is selected by the bit 4 of the opcode. a register indirect instruction is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long. 47
48/68 st62t52b st62t62b/e62b 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. the following par- agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory us- ing one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 16. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register d . affected * . not affected instruction addressing mode bytes cycles flags zc ld a, x short direct 1 4 d * ld a, y short direct 1 4 d * ld a, v short direct 1 4 d * ld a, w short direct 1 4 d * ld x, a short direct 1 4 d * ld y, a short direct 1 4 d * ld v, a short direct 1 4 d * ld w, a short direct 1 4 d * ld a, rr direct 2 4 d * ld rr, a direct 2 4 d * ld a, (x) indirect 1 4 d * ld a, (y) indirect 1 4 d * ld (x), a indirect 1 4 d * ld (y), a indirect 1 4 d * ldi a, #n immediate 2 4 d * ldi rr, #n immediate 3 4 * * 48
49/68 st62t52b st62t62b/e62b instruction set (contd) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc- tions one operand is always the accumulator while the other can be either a data space memory con- tent or an immediate value in relation with the ad- dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad- dresses. in com, rlc, sla the operand is al- ways the accumulator. table 17. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags zc add a, (x) indirect 1 4 dd add a, (y) indirect 1 4 dd add a, rr direct 2 4 dd addi a, #n immediate 2 4 dd and a, (x) indirect 1 4 dd and a, (y) indirect 1 4 dd and a, rr direct 2 4 dd andi a, #n immediate 2 4 dd clr a short direct 2 4 dd clr r direct 3 4 * * com a inherent 1 4 dd cp a, (x) indirect 1 4 dd cp a, (y) indirect 1 4 dd cp a, rr direct 2 4 dd cpi a, #n immediate 2 4 dd dec x short direct 1 4 d * dec y short direct 1 4 d * dec v short direct 1 4 d * dec w short direct 1 4 d * dec a direct 2 4 d * dec rr direct 2 4 d * dec (x) indirect 1 4 d * dec (y) indirect 1 4 d * inc x short direct 1 4 d * inc y short direct 1 4 d * inc v short direct 1 4 d * inc w short direct 1 4 d * inc a direct 2 4 d * inc rr direct 2 4 d * inc (x) indirect 1 4 d * inc (y) indirect 1 4 d * rlc a inherent 1 4 dd sla a inherent 2 4 dd sub a, (x) indirect 1 4 dd sub a, (y) indirect 1 4 dd sub a, rr direct 2 4 dd subi a, #n immediate 2 4 dd 49
50/68 st62t52b st62t62b/e62b instruction set (contd) conditional branch . the branch instructions achieve a branch in the program when the select- ed condition is met. bit manipulation instructions . these instruc- tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe- cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 18. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 d . affected. the tested bit is shifted into carry. ee. 8 bit signed displacement in the range -126 to +129 * . not affected table 19. bit manipulation instructions notes: b. 3-bit address; * . not affected rr. data space register; table 20. control instructions notes: 1. this instruction is deactivatedand a wait is automatically executed instead of a stop if the watchdog function is selected . d . affected *. not affected table 21. jump & call instructions notes: abc. 12-bit address; * . not affected instruction branch if bytes cycles flags zc jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrz e z = 1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * d jrs b, rr, ee bit = 1 3 5 * d instruction addressing mode bytes cycles flags zc set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags zc nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 dd stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags zc call abc extended 2 4 * * jp abc extended 2 4 * * 50
51/68 st62t52b st62t62b/e62b opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand 51
52/68 st62t52b st62t62b/e62b opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz4 jp2 jrnc4 res2 jrz2 ret2 jrc4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand 52
53/68 st62t52b st62t62b/e62b 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj=ta + pd x rthja where:ta = ambient temperature. rthja =package thermal resistance (junc- tion-to ambient). pd = pint + pport. pint =idd x vdd (chip internal power). pport =port power dissipation (determined by the user). notes: - stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. - (1) within these limits, clamping diodes are guarantee to be not conductive. voltages outside these limits are authorised as long as injection current is kept within the specification. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 (1) v v o output voltage v ss - 0.3 to v dd + 0.3 (1) v i o current drain per pin excluding v dd , v ss 10 ma iv dd total current into v dd (source) 50 ma iv ss total current out of v ss (sink) 50 ma tj junction temperature 150 c t stg storage temperature -60 to 150 c 53
54/68 st62t52b st62t62b/e62b 6.2 recommended operating conditions notes : 1. care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the a/d conversion. for a -1ma injection, a maximum 10 k w is recommended. 2. an oscillator frequency above 1mhz is recommended for reliable a/d results. figure 26. maximum operating frequency (fmax) versus supply voltage (v dd ) the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test conditions value unit min. typ. max. t a operating temperature 6 suffix version 1 suffix version 3 suffix version -40 0 -40 85 70 125 c v dd operating supply voltage f osc = 2mhz fosc= 8mhz 3.0 4.5 6.0 6.0 v f osc oscillator frequency 2) v dd = 3v v dd = 4.5v, 1 & 6 suffix v dd = 4.5v, 3 suffix 0 0 0 4.0 8.0 4.0 mhz i inj+ pin injection current (positive) v dd = 4.5 to 5.5v +5 ma i inj- pin injection current (negative) v dd = 4.5 to 5.5v -5 ma 8 7 6 5 4 3 2 1 2.533.544.555.56 supply voltage (v dd ) maximum frequency (mhz) functionality is not guaranteed in this area 3 suffix version 1 & 6 suffix version 54
55/68 st62t52b st62t62b/e62b 6.3 dc electrical characteristics (t a = -40 to +125c unless otherwise specified) notes: (1) hysteresis voltage between switching levels (2) all peripherals running (3) all peripherals in stand-by dc electrical characteristics (contd) (t a = -40 to +85c unless otherwise specified) symbol parameter test conditions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage (1) all input pins v dd = 5v v dd = 3v 0.2 0.2 v v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 3ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +7ma v dd = 5.0v; i ol = +15ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -3.0ma 4.9 3.5 v r pu pull-up resistance all input pins 40 100 200 kw reset pin 150 350 900 i il i ih input leakage current all input pins but reset v in = v ss (no pull-up configured) v in = v dd 0.1 1.0 m a input leakage current reset pin v in = v ss v in = v dd -8 -16 -30 10 i dd supply current in reset mode v reset =v ss f osc =8mhz 3.5 ma supply current in run mode (2) v dd =5.0v f int =8mhz, t a < 85c 6.6 ma supply current in wait mode (3) v dd =5.0v f int =8mhz, t a < 85c 1.5 ma supply current in stop mode (3) i load =0ma v dd =5.0v 20 m a symbol parameter test conditions value unit min. typ. max. v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 5ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +10ma v dd = 5.0v; i ol = +20ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -5.0ma 4.9 3.5 v i dd supply current in stop mode (3) i load =0ma v dd =5.0v 10 m a 55
56/68 st62t52b st62t62b/e62b 6.4 ac electrical characteristics (t a = -40 to +125c unless otherwise specified) notes : 1. period for which v dd has to be connected at 0v to allow internal reset function at next power-up. 2. sampled but not tested 6.5 a/d converter characteristics (t a = -40 to +125c unless otherwise specified) notes : 1. noise at av dd , av ss <10mv 2. with oscillator frequencies less than 1mhz, the a/d converter accuracy is decreased. symbol parameter test conditions value unit min. typ. max. t rec supply recovery time (1) 100 ms t wr minimum pulse width (v dd = 5v) reset pin nmi pin 100 100 ns t wee eeprom write time t a = 25c t a = 85c t a = 125c 5 10 20 10 20 30 ms endurance (2) eeprom write/erase cycle q a l ot acceptance 300,000 1 million cycles retention eeprom data retention t a = 55c 10 years c in input capacitance all inputs pins 10 pf c out output capacitance all outputs pins 10 pf symbol parameter test conditions value unit min. typ. max. res resolution 8 bit a tot total accuracy (1) (2) f osc > 1.2mhz f osc > 32khz 2 4 lsb t c conversion time f osc = 8mhz, t a < 85c f osc = 4mhz 70 140 m s zir zero input reading conversion result when v in = v ss 00 hex fsr full scale reading conversion result when v in = v dd ff hex ad i analog input current during conversion v dd = 4.5v 1.0 m a ac in analog input capacitance 2 5 pf 56
57/68 st62t52b st62t62b/e62b 6.6 timer characteristics (t a = -40 to +125c unless otherwise specified) 6.7 spi characteristics (t a = -40 to +125c unless otherwise specified) 6.8 artimer electrical characteristics (t a = -40 to +125c unless otherwise specified) symbol parameter test conditions value unit min. typ. max. f in input frequency on timer pin mhz t w pulse width at timer pin v dd = 3.0v v dd > 4.5v 1 125 m s ns f int 4 --------- - symbol parameter test conditions value unit min. typ. max. f cl clock frequency applied on scl 500 khz t su set-up time applied on sin 250 ns t h hold time applied onsin 50 ns symbol parameter test conditions value unit min typ max f in input frequency on artimin pin run and wait modes mhz stop mode 2 f int 4 --------- - 57
58/68 st62t52b st62t62b/e62b 7 general information 7.1 package mechanical data figure 27.16-pin plastic dual in line package (b), 300-mil width figure 28. 16-pin plastic small outline package (m), 300-mil width dim . mm inches min typ max min typ max a5.08.200 a1 .508 .020 b .381.508.533.015.020.021 b1 .762 1.651 .030 .065 c .203.254.304.008.010.012 d 18.92 19.18 19.56 .745 .755 .770 d1 1.27 .050 e 7.37 7.62 7.874 .290 .300 .310 e1 5.334 .210 k1 k2 l 2.997 3.302 3.708 .118 .130 .146 e 2.286 2.54 2.794 .090 .100 .110 number of pins dim . mm inches min typ max min typ max a 2.286 .090 a1 .102 .305 0.004 .012 b .381 .483 .015 .019 c .229 .254 .009 .010 d 10.26 10.34 .404 .407 d1------ e 10.24 10.34 .403 .407 e1 7.44 7.54 .293 .297 e2------ l.832 .033 e1.27 .050 h.508 .020 alpha 5 o 5 o number of pins 58
59/68 st62t52b st62t62b/e62b package mechanical data (contd) thermal characteristic 7.2 ordering information table 22. otp/eprom version ordering information symbol parameter test conditions value unit min. typ. max. rthja thermal resistance pdip16 55 c/w pso16 75 sales type program memory (bytes) eeprom (bytes) temperature range package st62e62bf1 1836 eprom 64 0 to +70c cdip16w st62t52bm6 st62t52bm3 1836 otp none -40 to + 85c -40 to + 125c pso16 st62t62bm6 st62t62bm3 1836 otp 64 -40 to + 85c -40 to + 125c pso16 59
60/68 st62t52b st62t62b/e62b notes: 60
april 1998 61/68 r st62p52b st62p62b 8-bit fastrom mcus with a/d converter, auto-reload timer and eeprom n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 64 bytes (none on st62t52b) n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input n 5 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n 8-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n user configurable power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 device rom (bytes) eeprom st62p52b 1836 - st62p62b 1836 64 61
62/68 st62p52b st62p62b 1 general description 1.1 introduction the st62p52b and st62p62b are the f actory a dvanced s ervice t echnique rom (fastrom) version of st62t52b and st62t62b otp devic- es. they offer the same functionality as otp devices, selecting as fastrom options the options de- fined in the programmable option byte of the otp version. 1.2 ordering information the following section deals with the procedure for transfer of customer codes to sgs-thomson. 1.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to sgs- thomson using the correctly filled option list appended. 1.2.2 listing generation and verification when sgs-thomson receives the users rom contents, a computer listing is generated from it. this listing refers exactly to the rom contents and options which will be used to produce the speci- fied mcu. the listing is then returned to the cus- tomer who must thoroughly check, complete, sign and return it to sgs-thomson. the signed list- ing forms a part of the contractual agreement for the production of the specific customer mcu. the sgs-thomson sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st62p52b/p62b table 2. fastrom version ordering information (*) advanced information device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector sales type rom eeprom (bytes) temperature range package st62p52bm1/xxx st62p52bm6/xxx st62p52bm3/xxx (*) 1836 bytes none 0 to +70c -40 to + 85c -40 to + 125c pso16 st62p62bm1/xxx st62p62bm6/xxx st62p62bm3/xxx (*) 1836 bytes 64 0 to +70c -40 to + 85c -40 to + 125c 62
63/68 st62p52b st62p62b st62p52b and st62p62b fastrom microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . sgs-thomson microelectronics references device: [ ] st62p52b [ ] st62p62b package: [ ] dual in line plastic [ ] small outline plastic with condionning: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0c to + 70c [ ] - 40c to + 85c oscillator source selection: [ ] crystal quartz/ceramic resonator [ ] rc network watchdog selection: [ ] software activation [ ] hardware activation power on reset delay [ ] 32768 cycle delay [ ] 2048 cycle delay readout protection: [ ] disabled [ ] enabled external stop mode control [ ] enabled [ ] disabled pb2-pb3 pull-up at reset [ ] enabled [ ] disabled comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . 63
64/68 st62p52b st62p62b notes: 64
april 1998 65/68 r st6252b st6262b 8-bit rom mcus with a/d converter, auto-reload timer, rom and eeprom n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 64 bytes (none on st62t52b) n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input n 5 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n 8-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n user configurable power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 device fastrom (bytes) eeprom st6252b 1836 - st6262b 1836 64 65
66/68 st6252b st6262b 1 general description 1.1 introduction the st6252b and st6262b are mask pro- grammed rom version of st62t52b and st62t62b otp devices. they offer the same functionality as otp devices, selecting as rom options the options defined in the programmable option byte of the otp version. figure 1. programming wave form 1.2 rom readout protection if the rom readout protection option is selected, a protection fuse can be blown to pre- vent any access to the program memory content. in case the user wants to blow this fuse, high volt- age must be applied on the test pin. figure 2. programming circuit note: zpd15 is used for overvoltage protection vr02001 0.5s min 15 10 5 14v typ 100 s max t t 4ma typ 100ma 150 s typ max test test vr02003 protect zpd15 5v v ss v dd test 47 f m 100nf 100nf 15v 14v 66
67/68 st6252b st6262b st6252b and st6262b microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . sgs-thomson microelectronics references device: [ ] st6252b [ ] st6262b package: [ ] dual in line plastic [ ] small outline plastic with condionning: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0c to + 70c [ ] - 40c to + 85c special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ " authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: dip16: 9 so16: 5 oscillator source selection: [ ] crystal quartz/ceramic resonator [ ] rc network watchdog selection: [ ] software activation [ ] hardware activation power on reset delay [ ] 32768 cycle delay [ ] 2048 cycle delay rom readout protection: [ ] disabled (fuse cannot be blown) [ ] enabled (fuse can be blown by the customer) note: no part is delivered with protected rom. the fuse must be blown for protection to be effective. external stop mode control [ ] enabled [ ] disabled pb2-pb3 pull-up at reset [ ] enabled [ ] disabled comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . 67
68/68 st6252b st6262b 1.3 ordering information the following section deals with the procedure for transfer of customer codes to sgs-thomson. 1.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected mask options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected mask options are communicated to sgs-thomson using the correctly filled op- tion list appended. 1.3.2 listing generation and verification when sgs-thomson receives the users rom contents, a computer listing is generated from it. this listing refers exactly to the mask which will be used to produce the specified mcu. the listing is then returned to the customer who must thorough- ly check, complete, sign and return it to sgs-thomson. the signed listing forms a part of the contractual agreement for the creation of the specific customer mask. the sgs-thomson sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st6252b/62b table 2. rom version ordering information information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification s mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pr eviously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or sy stems without the express written approval of sgs-thomson microelectronics. ? 1998 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector sales type rom eeprom (bytes) temperature range package ST6252BB1/xxx st6252bb6/xxx st6252bb3/xxx 1836 bytes none 0 to +70c -40 to + 85c -40 to + 125c pdip16 st6252bm1/xxx st6252bm6/xxx st6252bm3/xxx 0 to +70c -40 to + 85c -40 to + 125c pso16 st6262bb1/xxx st6262bb6/xxx st6262bb3/xxx 1836 bytes 64 0 to +70c -40 to + 85c -40 to + 125c pdip16 st6262bm1/xxx st6262bm6/xxx st6262bm3/xxx 0 to +70c -40 to + 85c -40 to + 125c pso16 68

▲Up To Search▲

Price & Availability of ST6252BB1

	To Download ST6252BB1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .